PIC18F44K20-I/MV【PDF 207/234 页】MCU 16KB FLASH 768B RAM 40-UQFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3875

203页 204页 205页 206页 [207页]208页 209页 210页 211页

dsPIC33F

DS70165E-page 72

Preliminary

2007 Microchip Technology Inc.

3.6

Interfacing Program and Data

Memory Spaces

The dsPIC33F architecture uses a 24-bit wide program

space and a 16-bit wide data space. The architecture is

also a modified Harvard scheme, meaning that data

can also be present in the program space. To use this

data successfully, it must be accessed in a way that

preserves the alignment of information in both spaces.

Aside from normal execution, the dsPIC33F architec-

ture provides two methods by which program space

can be accessed during operation:

Using table instructions to access individual bytes

or words anywhere in the program space

Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructions allow an application to read or write

to small areas of the program memory. This capability

makes the method ideal for accessing data tables that

need to be updated from time to time. It also allows

access to all bytes of the program word. The remap-

ping method allows an application to access a large

block of data on a read-only basis, which is ideal for

look ups from a large table of static data. It can only

access the least significant word of the program word.

3.6.1

ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program

spaces are 16 and 24 bits, respectively, a method is

needed to create a 23-bit or 24-bit program address

from 16-bit data registers. The solution depends on the

interface method to be used.

For table operations, the 8-bit Table Page register

(TBLPAG) is used to define a 32K word region within

the program space. This is concatenated with a 16-bit

EA to arrive at a full 24-bit program space address. In

this format, the Most Significant bit of TBLPAG is used

to determine if the operation occurs in the user memory

(TBLPAG<7> = 0) or the configuration memory

(TBLPAG<7> = 1).

For remapping operations, the 8-bit Program Space

Visibility register (PSVPAG) is used to define a

16K word page in the program space. When the Most

Significant bit of the EA is ‘1’, PSVPAG is concatenated

with the lower 15 bits of the EA to form a 23-bit program

space address. Unlike table operations, this limits

remapping operations strictly to the user memory area.

Table 3-37 and Figure 3-9 show how the program EA is

created for table operations and remapping accesses

from the data EA. Here, P<23:0> refers to a program

space word, whereas D<15:0> refers to a data space

word.

TABLE 3-37:

PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Access

Space

Program Space Address

<23>

<22:16>

<15>

<14:1>

<0>

Instruction Access

(Code Execution)

User

PC<22:1>

0xx

xxxx

xxxx xxx0

TBLRD/TBLWT

(Byte/Word Read/Write)

User

TBLPAG<7:0>

Data EA<15:0>

0xxx xxxx

xxxx xxxx xxxx xxxx

Configuration

TBLPAG<7:0>

Data EA<15:0>

1xxx xxxx

xxxx xxxx xxxx xxxx

Program Space Visibility

(Block Remap/Read)

User

PSVPAG<7:0>

Data EA<14:0>(1)

xxxx xxxx

xxx xxxx xxxx xxxx

Note 1:

Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式